Small electronic devices such as integrated circuits (IC) are prone to damage and failure from electro-static-discharges (ESD). Various ESD-protection structures have been placed near input, output, or bi-directional I/O pins of ICs. Many of these protection structures use passive components such as series resistors, diodes, and thick-oxide transistors. Another type of ESD structure uses an active transistor to safely shunt ESD current.
As manufacturing ability improves and device sizes shrink, lower voltages are applied to transistors during normal operation. These smaller transistors are much more susceptible to over-voltage failure but can operate with a lower power-supply voltage and thus consume less power and produce less heat.
Such smaller transistors are often placed in an internal “core” of an IC, while larger transistors with gate lengths that are above the minimum are placed around the core in the periphery. ESD-protection structures are placed in the periphery using these larger transistors.
Although internal nodes of the smaller core transistors do not connect directly with Input-Output pads of the IC, the inventors have realized that parts of ESD pulses may be capacitivly coupled to internal core transistors, causing unexpected damage in the core, despite ESD-protection structures in the periphery.
Thinner gate oxides of the core transistors can be shorted, and substrate junctions melted by relatively small capacitivly-coupled currents applied to the tiny core devices. Static charges from a person or machinery can produce such damaging currents that are only partially blocked by the input-protection circuits in the periphery.
FIG. 1 is a prior-art mixed-voltage chip with an ESD-protection circuit. Core circuitry 20 contains core transistors 24, 26 which have a small channel length and can be damaged by voltages that were considered normal voltages a few years ago. Core circuitry 20 receives a reduced power supply voltage VDDi from voltage regulator 14, which steps down the external power supply VDDx to a voltage that can be safely applied to core transistors 24, 26 and other transistors in core circuitry 20. For example, VDDx may be 5 volts and VDDi may be 3 volts, 1.8 volts, 1.2 volts, or some other value. There may be thousands of core transistors in core circuitry 20.
Core transistors 24, 26 drive transistors in level shifter 18, which also receives VDDi from voltage regulator 14. Level shifter 18 raises the high-level output voltage produced by core transistor 24 using VDDi from voltage regulator 14. The boosted high voltage from level shifter 18 is then applied to the gate of p-channel output transistor 12, allowing the output pad to be driven to VDDx, which is applied to the source of p-channel output transistor 12. Level shifter 18 also drives the gate of n-channel output transistor 10 to allow the output to be driven low.
Protection from ESD pulses is provided by grounded-gate transistor 30, which is an n-channel transistor with its gate, source, and substrate connected to ground. Grounded-gate transistor 30 can turn on to shunt the ESD pulse to ground, either by normal channel conduction for a negative ESD pulse, or by drain-to-source breakdown (avalanche breakdown of the parasitic NPN transistor). A thicker field-oxide may be used for the gate oxide of grounded-gate transistor 30 rather than the more damage-prone thin gate oxide.
When grounded-gate transistor 30 turns on, by shunting current to ground it can keep the voltage at the drains of output transistors 10, 12 below their breakdown voltage, protecting them as well as core circuitry 20 which are further protected by output transistors 10, 12 and level shifter 18. Thus core transistors 24, 26 in core circuitry 20 are well-protected.
Smaller gate lengths and device sizes are used for core transistors 24, 26 and others in core circuitry 20 while larger gate lengths and device sizes are used for output transistors 10, 12 and for grounded-gate transistor 30. The larger devices are less prone to ESD damage.
FIG. 2 shows a prior-art open drain chip. Rather than use push-pull output circuits that drive outputs both high and low, only a pull-down output driver may be used. A pull-up resistor can be added to the output, either on-chip or off-chip. Since n-channel output transistor 10 drives much more current than the pull-up transistor sources, when n-channel output transistor 10 turns on, node OUTPAD and the output pad are driven low. When n-channel output transistor 10 turns off, node OUTPAD and the output pad gradually rise in voltage due to the pull-up resistor.
Since there is no p-channel output transistor for the open-drain output, there is no need of level shifter 18 of FIG. 1. Core transistors 24, 26 can directly drive the gate of n-channel output transistor 10. Although voltage regulator 14 provides only VDDi to core circuitry 20, and thus the gate of n-channel output transistor 10 is driven high to VDDi rather than to VDDx, VDDi is sufficiently high to turn on n-channel output transistor 10 and drive the output low, although somewhat more slowly that if VDDx were applied.
ESD protection is still provided by grounded-gate transistor 30. However, with the absence of level shifter 18, core circuitry 20 is separated from output node OUTPAD by only the gate of n-channel output transistor 10.
ESD Failures of Core Transistors
The inventors have noticed that these kinds of open-drain chips are more susceptible to ESD damage than push-pull outputs such as shown in FIG. 1. While n-channel output transistor 10 has a larger gate length and does not get damaged by typical ESD pulses, core transistors 24, 26 use smaller gate lengths and other feature sizes and have been found to fail when n-channel output transistor 10 does not.
Protection for Standard ESD Pulses—FIGS. 3A-C
Static electricity that normally builds up on a person can discharge across the input pins or a semiconductor integrated circuit (IC or chip). IC chips are routinely tested for resistance to such electro-static-discharges (ESD) using automated testers that apply a voltage across different pairs of pins of the chip. Any pair of pins may be chosen for the ESD test. FIGS. 3A-C highlight normal, successful operation of an ESD-Protection circuit.
In FIG. 3A, grounded-gate transistor 30 is turned off during normal operation with typical power-supply and ground voltages. However, when a positive ESD pulse is applied between the pad (node OUTPAD) and ground, the large drain-to-source voltage causes avalanche breakdown to occur under the gate of grounded-gate transistor 30, and grounded-gate transistor 30 conducts current under its gate to ground through the parasitic NPN transistor. Other breakdown mechanisms may occur in grounded-gate transistor 30. However, the ESD pulse must produce a sufficiently high voltage on node OUTPAD to initiate this breakdown. Once breakdown begins, and the current flows from node OUTPAD to ground, a snap-back effect can occur wherein grounded-gate transistor 30 continues conducting at voltages that are less than the initial breakdown voltage. The current shunted through grounded-gate transistor 30 quickly reduces the voltage on node OUTPAD, protecting core circuitry 20.
VDDi is generated by voltage regulator 14 using comparator 28 to compare VDDi to a reference voltage Vref and adjust the resistance of regulator transistor 22.
FIG. 3B shows a graph of the voltage on node OUTPAD over time as an ESD pulse is applied, while FIG. 3C shows that internal node NG has a lower voltage pulse that is coupled by parasitic Miller capacitor 32 from node OUTPAD to node NG. Capacitor 32 is formed from the gate-to-drain overlap of n-channel output transistor 10 and can be substantial when n-channel output transistor 10 is a large transistor designed to drive a large external load. This Miller capacitance is considered parasitic, and other parasitic capacitances may be included in capacitor 32.
Grounded-gate transistor 30 is designed to pass industry-standard ESD tests. These tests generate ESD pulses based on models such as the ESD machine model, which creates the ESD pulse by discharging a 200-pF capacitor that was charged to 100-400 volts, or the ESD human-body model, which creates the ESD pulse by discharging a 100-pF capacitor that was charged to 1000-4000 volts. The human-body model discharges the capacitor through a 1.5 k-ohm resistor, which limits the peak current in the pulse but extends the duration of the pulse.
Since the current of both the ESD human model (HBM) and the machine model (MM) are discharged from a small 100 or 200 pF capacitor, the duration of the discharged current is very short.
Protection Fails for Non-Standard ESD Pulses—FIGS. 4A-C
However, some real-world ESD pulses are longer in duration and/or lower in voltage than the HBM. Core transistor 26 in core circuitry 20 can be burned out by electro-over-stress (EOS) pulses that are low voltage but higher current (100 ma above) with long duration. These kinds of pulses can be generated in real-world hot-swap interfaces for telecom and datacom applications.
FIGS. 4A-C highlight failure of an ESD-Protection circuit when a non-standard ESD pulse occurs. When the ESD pulse is of longer duration than for the HBM, the peak voltage created by the ESD pulse may be reduced. Sometimes the ESD pulse has a lower voltage that what is created by the HBM or a standard ESD testing machine.
It is surprising that a lower-voltage ESD pulse could cause failures when a higher-voltage ESD pulse protects against failures. It is counter-intuitive that a lower voltage causes failures when a higher voltage does not. However, the inventors have observed this unusual phenomenon.
In FIG. 4A, damage is seen in core transistor 26 when n-channel output transistor 10 and grounded-gate transistor 30 do not show damage. This core damage occurs when a lower-voltage ESD pulse such as that shown in FIG. 4B is applied to the pad and node OUTPAD compared to FIG. 3B, when the standard ESD pulse is applied, producing a higher voltage on node OUTPAD.
The inventors theorize that the lower voltage applied to node OUTPAD by the sub-standard ESD pulse is below the breakdown voltage and thus insufficient to turn on grounded-gate transistor 30. It is also possible that grounded-gate transistor 30 does eventually turn on, but later than usual, allowing time for core transistor 26 to be damaged.
The lower-voltage pulse on node OUTPAD prevents or delays turn-on of grounded-gate transistor 30, so no current is shunted to ground. Instead, the voltage on node OUTPAD rises and this rise in voltage is capacitivly coupled through parasitic Miller capacitor 32 to node NG.
The rise in voltage of node NG may seem to be small, but the small device sizes of core transistors 24, 26 may be quite sensitive to voltages above VDDi. This slight voltage rise on node NG may be sufficient to damage core transistors 24, 26 as observed by the inventors.
FIG. 4C shows that the voltage of internal node NG rises slightly higher and for a longer period of time than for the standard ESD pulse test of FIG. 3C. The exact voltages of internal node NG are not known but are here theorized by the inventors.
The amount that the voltage of node NG rises compared with the rise of node OUTPAD depends on the capacitive coupling ratio of parasitic Miller capacitor 32. When n-channel output transistor 10 is large, parasitic capacitor 32 is also large, while drain capacitances of core transistors 24, 26 may be much smaller. This combination produces a relatively large coupling ratio, increasing the voltage of the pulse on node NG.
FIGS. 5A-D are graphs comparing operating conditions for standard high-voltage ESD tests and sub-standard lower-voltage ESD tests. A standard ESD test is shown in FIGS. 5A-B.
FIG. 5A shows a current-voltage curve. As the ESD pulse is applied to the pad at node OUTPAD, initially grounded-gate transistor 30 is turned off so the current is low as the voltage rises from the origin. Once the voltage is above the avalanche breakdown voltage VTO, current increases dramatically as the voltage is reduced (snaps back) as current flow continues to increase. Core transistor 26 likewise conducts in a snap-back mode once the ESD pulse is coupled through parasitic Miller capacitor 32 to its drain. The current through core transistor 26 is much less than through grounded-gate transistor 30.
FIG. 5B shows a voltage-time plot of the pad node and internal nodes when the standard ESD pulse is applied. The ESD pulse raises the voltage of pad node OUTPAD to a high level that is above the breakdown voltage VTO. Some of this voltage rise is coupled through parasitic Miller capacitor 32 to the drain of core transistors 24, 26. However, once grounded-gate transistor 30 turns on, the voltage pulse on node OUTPAD drops quickly, cutting the width of the pulse on internal node NG. If grounded-gate transistor 30 turns on quickly enough, the pulse on internal node NG does not have time to reach higher voltages that could damage core transistors 24, 26. The voltage stays below the avalanche breakdown voltage of core transistors 24, 26, VTC.
FIG. 5C shows a current-voltage curve when a lower voltage pulse is applied. As the sub-standard ESD pulse is applied to the pad at node OUTPAD, initially grounded-gate transistor 30 is turned off so the current is low as the voltage rises from the origin. Once the voltage is above the breakdown voltage, current increases as the voltage is reduced (snaps back) as current flow continues to increase. However, grounded-gate transistor 30 turns on more slowly with the lower ESD pulse. Core transistor 26 turns on earlier than for FIG. 5A and snaps-back once the ESD pulse is coupled through parasitic Miller capacitor 32 to its drain. Since core transistor 26 has a shorter gate length than does grounded-gate transistor 30, it snaps back more dramatically as seen in FIG. 5C. The current through core transistor 26 is much closer to that than through grounded-gate transistor 30 in FIG. 5C than in FIG. 5A.
FIG. 5D shows a voltage-time plot of the pad node and internal nodes when the sub-standard ESD pulse is applied. The sub-standard ESD pulse raises the voltage of pad node OUTPAD to a moderate level that is initially below the breakdown voltage VTO. Some of this voltage rise is coupled through parasitic Miller capacitor 32 to the drain of core transistors 24, 26. Node NG reaches a higher voltage level in FIG. 5D than in FIG. 5B since grounded-gate transistor 30 is delayed in turning on by the sub-standard ESD pulse. The voltage rises above the avalanche breakdown voltage of core transistors 24, 26, VTC. The higher NG voltage and its longer duration breaks down core transistor 26, causing irreversible damage to core circuitry 20 when the voltage at node NG exceeds the core transistors' second breakdown voltage.
Once grounded-gate transistor 30 turns on, the voltage pulse on node OUTPAD drops, cutting the width of the pulse on internal node NG. However, since grounded-gate transistor 30 turns on too slowly, or never turns on, the pulse on internal node NG was wider in duration and had time to reach higher voltages that damage core transistors 24, 26. Thus the wider, longer NG pulse in FIG. 5D compared with FIG. 5B is thought to cause the damage seen on core transistor 26. After avalanche breakdown occurs, thermal runaway breakdown can next occur, causing permanent damage.
What is desired is an electro-static-discharge (ESD) protection circuit that can protect against damage from sub-standard ESD pulses. An improved ESD protection circuit that protects against both high and lower-voltage ESD pulses is desirable.